1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of Related Art
An increase of the density of a metal oxide semiconductor field effect transistor (MOSFET) is making it difficult to arrange a gate, a source, and a drain as components of a MOSFET on a plane. A three-dimensional layout has been required in a dynamic random access memory (DRAM) having a minimum wiring pitch of 90 nm or less. Such a three-dimensional layout refers to a structure in which a source and a drain (S/D) are formed at an upper end and a lower end of a pillar of a semiconductor extending in a direction perpendicular to a principal plane of a semiconductor substrate (in a normal direction to a principal plane of a semiconductor substrate), a gate insulator film and a gate electrode (word line) are arranged on a surface of an intermediate portion of the pillar, and those components are stacked on the principal plane of the semiconductor substrate. In the following description, a transistor having such a structure is referred to as a vertical transistor. A pillar of a semiconductor as described above is referred to as a semiconductor pillar. In a case where a semiconductor is silicon, a pillar of a semiconductor is referred to as a silicon pillar. An example of a vertical transistor is disclosed in JP-A 2008-311641 (Patent Document 1).